1. Field of the Invention
The present invention is related to wire-OR matching circuits, and particularly to a low-power wire-OR matching circuit.
2. Description of the Prior Art
In Dynamic Random Access Memory (DRAM), a wire-OR matching circuit may be used to determine whether a memory unit to be accessed is a damaged memory unit according to an access address. When the wire-OR matching circuit determines that the access address is the same as the address of the damaged memory unit, the wire-OR matching circuit enables a backup memory unit to replace the known damaged memory unit, so that the DRAM can be accessed normally.
Please refer to FIG. 1. FIG. 1 is a diagram of wire-OR matching circuit 100. Wire-OR matching circuit 100 comprises an input inverter INV1, an output inverter INV2, and a disabling module 110. Input node I of input inverter INV1 receives input-enabling signal SENI, and determines whether to generate output-enabling signal SENO at output node O of output inverter INV2 according to state of disabling module 110. Additionally, in wire-OR matching circuit 100, when input-enabling signal SENI and output-enabling signal SENO are logic 0 (low voltage), input-enabling signal SENI and output-enabling signal SENO represent “enabled”. When input-enabling signal SENI and output-enabling signal SENO are logic 1 (high voltage), input-enabling signal SENI and output-enabling signal SENO represent “disabled”.
Input inverter INV1 is used for inverting input-enabling signal SENI to output middle signal SMI. Input inverter INV1 comprises transistors QP1, QN1. Transistor QP1 can be realized as a P-channel metal oxide semiconductor (PMOS) transistor, and transistor QN1 can be realized as an N-channel metal oxide semiconductor (NMOS) transistor. As shown in FIG. 1, first node 1 of transistor QP1 is power node PW1 of input inverter INV1, which is coupled to voltage source VDD; second node 2 of transistor QP1 is coupled to output node O of input inverter INV1; and control node (gate) C of transistor QP1 is coupled to input node I of input inverter INV1. First node 1 of transistor QN1 is coupled to output node O of input inverter INV1; second node 2 of transistor QN1 is power node PW2 of input inverter INV1, which is coupled to voltage source VSS; and control node (gate) C of transistor QN1 is coupled to input node I of input inverter INV1. Additionally, voltage source VDD supplies voltage VDD (high voltage); and voltage source VSS supplies voltage VSS (low voltage, e.g. ground). When input inverter INV1 receives input-enabling signal SENI representing “enabled” (logic 0, low voltage), transistor QP1 conducts, so that output node O of input inverter INV1 couples to voltage source VDD through transistor QP1. Thus, voltage on output node O of input inverter INV1 is pulled up to high voltage and outputs middle signal SMI representing logic 1 (high voltage); when input inverter INV1 receives input-enabling signal SENI representing “disabled” (logic 1, high voltage), transistor QN1 conducts, so that output node O of input inverter INV1 couples to voltage source VSS through transistor QN1. Thus, voltage on output node O of input inverter INV1 is pulled down to low voltage and outputs middle signal SMI representing logic 0 (low voltage).
Output inverter INV2 is used for inverting middle signal SMI to generate output-enabling signal SENO. When middle signal SMI represents logic (high voltage), output inverter INV2 outputs output-enabling signal SENO representing “enabled” (logic 0, low voltage). When middle signal SMI represents logic 0 (low voltage), output inverter INV2 outputs output-enabling signal SENO representing “disabled” (logic 1, high voltage).
Disabling module 110 comprises switches SW1-SWM. Control nodes C of switches SW1-SWM respectively receive sub-control signals SC1-SCM comprised by control signals SC; first nodes 1 of switches SW1-SWM are all coupled to output node O of input inverter INV1; second nodes of switches SW1-SWM are all coupled to voltage source VSS. Each switch SW1-SWM couples its first node 1 to its second node 2 according to the sub-control signal received. For example, switches SW1-SWM may be realized as NMOS transistors. Thus, when sub-control signal SCK is logic 1 (high voltage), sub-control signal SCK represents “turn on,” such that first node 1 of switch SWK couples to second node 2 of switch SWK; when sub-control signal SCK is logic 0 (low voltage), sub-control signal SCK represents “turn off,” such that first node 1 of switch SWK does not couple to second node 2 of switch SWK.
When control signal SC represents “disabled,” it means that at least one sub-control signal (e.g. sub-control signal SCK) of the sub-control signals SC1-SCM indicates “turn on.” Thus, in the disabling module 110, first node 1 of switch SWK corresponding to sub-control signal SCK is coupled to second node 2 of switch SWK. In this way, output node O of input inverter INV1 couples to voltage source VSS through switch SWK, causing middle signal SMI to be pulled down to low voltage (logic 0) by voltage source VSS. Thus, when control signal SC represents “disabled,” disabling module 110 controls middle signal SMI outputted by input inverter INV1 to represent logic 0 (low voltage). However, when control signal SC represents “not disabled,” it means that all sub-control signals SC1-SCM are “turn off,” so none of the switches SW1-SWM conducts. In this way, disabling module 110 does not affect logic represented by middle signal SMI.
In wire-OR matching circuit 100, when input-enabling signal SENI represents “enabled,” disabling module 110 determines whether or not to control logic represented by middle signal SMI according to control signal SC, so as to disable output inverter INV2. For example, assume input-enabling signal SENI representing “enable” is inputted to wire-OR matching circuit 100. If a memory address to be accessed in DRAM is different from a known corrupted memory address, control signal SC will represent “disabled.” Thus, regardless of whether the input-enabling signal SENI received by input inverter INV1 represents “enabled” or “disabled,” disabling module 110 will control logic represented by middle signal SMI to be 0, so as to disable output inverter INV2, and make output inverter INV2 output output-enabling signal SENO as “not enabled.” Thus, wire-OR matching circuit 110 will not enable backup memory. However, if the memory address to be accessed in DRAM is the same as a known corrupted memory address, control signal SC will represent “not disabled.” Thus, disabling module 110 will not affect logic represented by middle signal SMI, so that output inverter INV2 can output output-enabling signal SENO representing “enabled” according to middle signal SMI representing logic 1 under condition that input-enabling signal SENI represents “enabled” (logic 0). In this way, wire-OR matching circuit 110 can enable backup memory to replace corrupted memory, so that DRAM can be accessed normally.
Please refer to FIG. 2. FIG. 2 is a waveform diagram illustrating internal control signals of wire-OR matching circuit 100 when input-enabling signal SENI represents “enabled,” and control signal SC represents “disabled” (e.g. when at least one sub-control signal of sub-control signals SC1-SCM represents “turn on”). Current IL is current outputted by output node O of inverter INV1 of FIG. 1. Assume that sub-control signal SCK of sub-control signals SC1-SCM represents “turn on” (logic 1, high voltage). Thus, output node O of input inverter INV1 will couple to voltage source VSS through switch SWK, and output node O of input inverter INV1 will be pulled down to low voltage by voltage source VSS, and output middle signal SMI representing logic 0. Thus, output inverter INV2 will output output-enabling signal SENO as “not enabled.”
However, when input-enabling signal SENI represents “enabled” (logic 0, low voltage), output node O of input inverter INV1 will be coupled to voltage source VDD through transistor QP1. In other words, voltage source VDD will couple to voltage source VSS through transistor QP1 of input inverter INV1 and switch SWK. Thus, current IL will become a large current because voltage source VDD couples to voltage source VSS. It can be seen that, in wire-OR matching circuit 100, when control signal SC represents “disabled” and input-enabling signal SENI represents “enabled,” voltage source VDD will couple to voltage source VSS through input inverter INV1, generate high current, and cause high power consumption, which is a great inconvenience to the user.